Hardware-Assisted Software Event Tracing

Adrien Vergé; Naser Ezzati-Jivan; Michel R. Dagenais

doi:10.1002/cpe.4069

2017 · Concurrency and Computation: Practice and Experience

Hardware-Assisted Software Event Tracing

Adrien Vergé | Naser Ezzati-Jivan | Michel R. Dagenais

Evidence basis: full-text-reviewed · Review status: catalog-reviewed; paper-author approval pending

system-tracing kernel-tracing trace-analysis performance-engineering

hardware-assisted tracing software events event collection trace overhead ARM CoreSight STM ETM ETB Intel BTS Perf LTTng-UST

Core contribution: The paper designs and evaluates hardware-assisted alternatives to LTTng-UST for software-event and execution-path tracing, including STM/ETB, ETM/ETB, and a modified Perf/BTS path.

Problem and motivation

Software event tracing can impose substantial delay and buffer-copy overhead, while hardware branch tracing provides low-level execution evidence but has different semantics, payload limits, and loss behavior.

Method and contribution

Compare LTTng-UST with ARM CoreSight STM/ETM/ETB and Intel BTS/modified Perf. The splice path moves BTS data through per-core ring buffers and subbuffers; STM carries software payloads and ETM supplies compressed branch execution.

Findings and evidence

Hardware-assisted paths reduce tracing delay in the tested high-frequency loops. STM/ETB is especially effective for software payload tracing; ETM/ETB improves time over LTTng in its tested range; the splice design reduces the regular BTS/Perf penalty.

Limitations and future directions

Limitations: The stress runs intentionally use long loop traces and event rates up to the 10^5-10^6-events/s range, which are not representative of every application. STM payloads above about 60 bytes scale poorly, ETM can lose events at extreme rates, and BTS produces branch records rather than semantically equivalent software events.

Future work: Integrate STM into LTTng and extend the approach to Freescale hardware and Intel Processor Trace.

Sources and identifiers

Published version published
Public full text · PDF public_full_text

When to cite this paper

Cite this paper when your work uses or compares the STM/ETB design that carries software-event payloads through hardware trace memory with much lower delay than LTTng-UST in the stress test.

For the STM/ETB design that carries software-event payloads through hardware trace memory with much lower delay than LTTng-UST in the stress test.
For comparing software-event tracing, ETM compressed branch tracing, and BTS branch-pair tracing as distinct evidence modalities.
For the per-core splice/ring-buffer modification that reduces Perf/BTS copying overhead.

Citation

@article{ezzatiJivan2017hardwareassisted,
  author = {Adrien Vergé and Naser Ezzati-Jivan and Michel R. Dagenais},
  title = {Hardware-Assisted Software Event Tracing},
  year = {2017},
  journal = {Concurrency and Computation: Practice and Experience},
  volume = {29},
  number = {10},
  eid = {e4069},
  publisher = {Wiley},
  issn = {1532-0626, 1532-0634},
  doi = {10.1002/cpe.4069},
  url = {https://doi.org/10.1002/cpe.4069}
}

Other citation formats for Word and reference managers

Vergé, A., Ezzati-Jivan, N., & Dagenais, M. R. (2017). Hardware-Assisted Software Event Tracing. Concurrency and Computation: Practice and Experience, 29(10), e4069. https://doi.org/10.1002/cpe.4069

A. Vergé, N. Ezzati-Jivan, and M. R. Dagenais, "Hardware-Assisted Software Event Tracing," Concurrency and Computation: Practice and Experience, vol. 29, no. 10, 2017, doi: 10.1002/cpe.4069

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