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  "paper_id": "hardware-assisted-software-event-tracing",
  "page_url": "https://naser.github.io/research-publications/papers/hardware-assisted-software-event-tracing/",
  "title": "Hardware-Assisted Software Event Tracing",
  "title_variants": [],
  "authors": [
    "Adrien Vergé",
    "Naser Ezzati-Jivan",
    "Michel R. Dagenais"
  ],
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      "name": "Adrien Vergé",
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    {
      "name": "Naser Ezzati-Jivan",
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    {
      "name": "Michel R. Dagenais",
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  "publication": {
    "year": 2017,
    "venue": "Concurrency and Computation: Practice and Experience",
    "type": "journal article",
    "publication_date": "2017-03-06",
    "online_date": "2017-03-06",
    "print_date": "2017-05-25",
    "volume": "29",
    "issue": "10",
    "pages": null,
    "article_number": "e4069",
    "publisher": "Wiley",
    "issn": [
      "1532-0626",
      "1532-0634"
    ],
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  "source_record_id": "hardware-assisted-software-event-tracing-adde2d2e93",
  "identifiers": {
    "doi": "10.1002/cpe.4069"
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  "abstract": null,
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  "description": "The paper designs and evaluates hardware-assisted alternatives to LTTng-UST for software-event and execution-path tracing, including STM/ETB, ETM/ETB, and a modified Perf/BTS path.",
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  "evidence": {
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    "verified_on": "2026-08-09",
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      },
      {
        "note": "author identity matched to Naser Ezzati-Jivan in the local research catalog"
      },
      {
        "note": "Hardware-assisted tracing PDF pp. 1-4: problem, ARM CoreSight/Intel BTS design, platforms, and LTTng comparison"
      },
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        "note": "Hardware-assisted tracing PDF pp. 4-10: STM/ETM/BTS implementations, benchmark results, and modified Perf path"
      },
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  "summary": {
    "core_contribution": "The paper designs and evaluates hardware-assisted alternatives to LTTng-UST for software-event and execution-path tracing, including STM/ETB, ETM/ETB, and a modified Perf/BTS path.",
    "problem": "Software event tracing can impose substantial delay and buffer-copy overhead, while hardware branch tracing provides low-level execution evidence but has different semantics, payload limits, and loss behavior.",
    "method": "Compare LTTng-UST with ARM CoreSight STM/ETM/ETB and Intel BTS/modified Perf. The splice path moves BTS data through per-core ring buffers and subbuffers; STM carries software payloads and ETM supplies compressed branch execution.",
    "findings": "Hardware-assisted paths reduce tracing delay in the tested high-frequency loops. STM/ETB is especially effective for software payload tracing; ETM/ETB improves time over LTTng in its tested range; the splice design reduces the regular BTS/Perf penalty.",
    "limitations": "The stress runs intentionally use long loop traces and event rates up to the 10^5-10^6-events/s range, which are not representative of every application. STM payloads above about 60 bytes scale poorly, ETM can lose events at extreme rates, and BTS produces branch records rather than semantically equivalent software events.",
    "future_work": "Integrate STM into LTTng and extend the approach to Freescale hardware and Intel Processor Trace."
  },
  "tags": [
    "system-tracing",
    "kernel-tracing",
    "trace-analysis",
    "performance-engineering"
  ],
  "keywords": [
    "hardware-assisted tracing",
    "software events",
    "event collection",
    "trace overhead",
    "ARM CoreSight",
    "STM",
    "ETM",
    "ETB",
    "Intel BTS",
    "Perf",
    "LTTng-UST"
  ],
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      "title": "Hardware-Assisted Software Event Tracing",
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    "license": null
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  "citation_guidance": {
    "when_to_cite": "Cite this paper when your work uses or compares the STM/ETB design that carries software-event payloads through hardware trace memory with much lower delay than LTTng-UST in the stress test.",
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      "For the STM/ETB design that carries software-event payloads through hardware trace memory with much lower delay than LTTng-UST in the stress test.",
      "For comparing software-event tracing, ETM compressed branch tracing, and BTS branch-pair tracing as distinct evidence modalities.",
      "For the per-core splice/ring-buffer modification that reduces Perf/BTS copying overhead."
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      "author identity matched to Naser Ezzati-Jivan in the local research catalog",
      "Hardware-assisted tracing PDF pp. 1-4: problem, ARM CoreSight/Intel BTS design, platforms, and LTTng comparison",
      "Hardware-assisted tracing PDF pp. 4-10: STM/ETM/BTS implementations, benchmark results, and modified Perf path",
      "Hardware-assisted tracing PDF p. 10: conclusion, quantitative comparisons, and limitations",
      "local PDF hash verified in pdf-evidence/extraction-manifest.json"
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    "summary_written_by": "AI-assisted",
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